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o2109 sy 20091008-s00002 no.1582-1/12 LE24C043 ordering number : ena1582 cmos ic two wire serial interface eeprom (4k eeprom) overview the LE24C043 is a 2-wire serial interface 4k bit eeprom. it realizes high speed and a high level reliability by incorporating sanyo?s high performance cmos eeprom technology. this device is compatible with i 2 c memory protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory. functions ? capacity: 4k bits (256 8 bits) ? single supply voltage: 2.7v to 5.5v ? interface: two wire serial interface (i 2 c bus*) ? operating clock frequency: 400khz ? low power consumption : standby: 2 a (max) : active (read): 0.5ma (max) ? automatic page write mode: 16 bytes ? read mode: sequential read and random read ? erase/write cycles: 10 6 cycles ? data retention: 20 years ? high reliability: adopts sanyo?s proprietary sy mmetric memory array configuration (usp6947325) noise filters connected to scl and sda pins incorporates a feature to prohibit write operations under low voltage conditions. ? package : mfp8(225mil) LE24C043m * i 2 c bus is a trademark of philips corporation. * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LE24C043 package dimensions unit:mm (typ) 3032d [LE24C043m] sanyo : mfp8(225mil) 14 85 5.0 0.63 6.4 0.15 0.35 1.27 (0.65) 4.4 (1.5) 1.7max 0.1 pin assignment pin descriptions pin.1 nc nonconnected pin pin.2 nc nonconnected pin pin.3 nc nonconnected pin pin.4 gnd ground pin.5 sda serial data input pin.6 scl serial clock input/output pin.7 wp write protect pin.8 v dd power supply nc nc nc gnd v dd wp scl sda 1 2 3 4 8 7 6 5 block diagram eeprom array x decoder high voltage generator serial-parallel converter address generator y decoder & sense amp condition detector i/o buffer input buffer serial controller scl sda write controller wp no.1582-2/12
LE24C043 specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage -0.5 to +6.5 v dc input voltage -0.5 to +5.5 v over-shoot voltage below 20ns -1.0 to +6.5 v storage temperature tstg -65 to +150 c note: if an electrical stress exceeding the maximu m rating is applied, the device may be damaged. operating conditions parameter symbol conditions ratings unit operating supply voltage 2.7 to 5.5 v operating temperature -40 to +85 c dc electrical characteristics v dd =2.7v to 5.5v parameter symbol conditions min typ max unit supply current at reading i cc 1 f=400khz 0.5 ma supply current at writing i cc 2 f=400khz, t wc =10ms 3 ma cmos standby current i sb v in =v dd or v ss 2 a input leakage current i li v in =gnd to v dd -2 2 a output leakage current i lo v in =gnd to v dd -2 2 a input low voltage v il v dd *0.2 v input low voltage (cmos) v ilc 0.2 v input high voltage v ih v dd *0.8 v input high voltage (cmos) v ihc v dd -0.2 v i ol =0.7ma, v dd =2.7v 0.2 v output low voltage v ol i ol =2.0ma, v dd =2.7v 0.4 v capacitance /ta=25 c, f=1mhz parameter symbol conditions max unit input pin capacitance c i v in =0v (other than sda) 10 pf in/output pin capacitance c i/o v i/o =0v (sda) 10 pf note: this parameter is sampled and not 100% tested. ac electric characteristics r=3.0k sda v dd c=50pf input pulse level 0.1 v dd to 0.9 v dd input pulse rise / fall time 20ns output detection voltage 0.5 v dd output load 50pf+pull up resistor 3.0k output load circuit no.1582-3/12
LE24C043 v dd =2.7v to 5.5v parameter symbol min typ max unit slave mode scl clock frequency f scls 0 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 n s stop condition setup time t su.sto 600 ns scl sda rise time t r 300 ns scl sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write cycle time t wc 10 ms bus timing no.1582-4/12 sda/in write timing scl sda/out t buf t su.sto t r t su.sta t hd.dat t high t low t su.dat t dh t aa t f t hd.sta t sp t sp write data acknowledge stop condition start condition t wc scl sda d0
LE24C043 no.1582-5/12 pin functions scl (serial clock input/output) pin the scl pin is a serial clock input pin that processes signals at the rising and falling edges of scl clock signals. sda pin must be pulled up by a resistor to the v dd level and wired-ored with an open drain (or open collector) output device for use. sda (serial data input/output) pin the sda pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl pin, the sda pin must be pulled up by a resistor to the v dd level and wired-ored with an open drain (or open collector) output device for use. wp (write protect) pin when the wp pin is high, write protection is enabled, and writing into the all memory areas is prohibited. when the pin is low, writing is possible to all memory areas. read operations can be performed regardless of the wp pin status.
LE24C043 functional description 1 start condition when the scl line is at the high level, the start condition is established by changing the sda line from high to low. the operation of the eeprom as a slave starts in the start condition. 2 stop condition when the scl line is at the high level, the stop condition is established by changing the sda line from low to high. when the device is set up for the read sequence, the read operation is suspended when th e stop condition is received, and the device is set to standby mode. when it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the eeprom internal write operation is started. stop condition start condition scl sda t su.sta t hd.sta t su.sto 3 data transfer data is transferred by changing the sd a line while the scl line is low. when the sda line is changed while the scl line is high, the resulting condition will be recognized as the start or stop condition. scl sda t su.dat t hd.dat 4 acknowledge during data transfer, 8-bits are transferred in succession, and then in th e ninth clock cycle period the device on the system bus receiving the data sets the sda line to low, and sends the acknowledge signal indicating that the data has been received. the ackn owledge signal is not sent during an eeprom internal write operation. acknowledge bit output start condition scl (eeprom input) sda (master output) sda (eeprom output) 1 8 9 t aa t dh no.1582-6/12
LE24C043 5 device addressing for the purposes of communication, the master device in the system generates the start condition for the slave device. communication with a particular slave device is enabled by sending along the sda bus the device address, which is 7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. the upper four bits of the device address are called the device code which, for this product, is fixed as ?1010.? this device has the upper 2-bit of the slave device address as the slave address (s1, s2), which fixed on the inside. the value of slave address are s1=0, s2=0. when the device code input from sda and the slave addresse s are compared with the pro duct?s device code and slave addresses that were set at the mounti ng stage and found to match, the product sends the acknowledge signal during the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command code. if they do not match, the eeprom returns to standby mode. when a read operation is performed immediately after the slave device has been switched, the random read command must be used. no.1582-7/12 1 0 1 0 s2 s1 a8 r/w device code slave address msb lsb device address word memory address
LE24C043 6 eeprom write operation 6-1. byte writing when the eeprom receives the 7-bit device address an d write command code "0" after the start condition, it generates an acknowledge signal. after this, if it 8-bit word address, generates an acknowledge signal, receives the 8- bit writing data, and generates an acknow ledge signal when it receives the stop condition, the rewrite operation of the eeprom in the designated memory address w ill start. rewriting is completed in the t wc period after the stop condition. during an eeprom rewrite op eration, no input is accepted and no acknowledge signals are generated. sda word address 0 1 0 s1 1 w start ack ack ack stop d7 d6 d5 d4 d3 d2 d1 d0 data r/w s2 a7 a6 a5 a4 a3 a2 a1 a0 a8 6- 2. pa ge wri t i ng th is p r od u c t en ab les p a g e s with up to 16 b y tes to b e written. th e b a sic d a t a tran sfer pro c ed ure is t h e same as for b y te writing : fo llowing th e start co nd itio n, the 7 - b it d e v i ce ad dr ess and write co mman d co de ?0 ,? wo rd add r ess (n ), an d d a ta (n ) are inpu t in t h is o r d e r wh ile co nfirm i n g ackno wled ge ?0 ? ev ery 9 bits. th e p a g e write m o d e is estab lish e d if, after d a ta (n) is in pu t, t h e writ e d a ta (n +1 ) is in pu t w ithou t i n pu ttin g th e sto p cond itio n . after th is, th e write d a ta equi valent t o t h e largest page size can be rec e ived by a c o nt inuous process of re peatin g t h e receivi ng of t h e 8-bit write d a ta and g e n e rating th e ack nowledg e sig n a ls. at th e po in t wh en th e write data (n +1 ) h a s been inpu t, t h e l o we r 4 bi t s ( a 0- a3 ) of t h e w o r d a d dresse s a r e autom a tically increm ented to form the (n + 1 ) addres s. in thi s way, t h e writ e data ca n be s u ccessively i n put, a n d the word a d dress on the pa ge is increm ente d each tim e the write data is i n put. if t h e write data excee ds 32 bytes or t h e last ad dress of th e p a g e is ex ceed ed, th e word ad dress on t h e p a g e is ro lled ov er. write data will b e i n pu t in to t h e sam e ad d r ess t w o or m o re times, bu t in su ch cases th e write d a ta th at was inp u t last will tak e effect. fi n a lly, th e eeprom i n ternal write opera tion c o rres p onding to the pa ge size for whic h the wr ite dat a is received starts from the d e sign ated m e m o ry ad d r ess wh en t h e st o p co nd itio n is receiv e d . ack stop d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 ack ack ??? da t a(n+ x) ack ack sda 0 1 0 s1 1 w start ack ack ack d7 d6 d5 d4 d3 d2 d1 d0 data(n ) r/w s2 a7 a6 a5 a4 a3 a2 a1 a0 a8 word address(n ) d7 d6 d1 d0 data(n+1 ) ack 6- 3. ac k n o w l e dge p o l l i ng ackno wled g e p o lling is u s ed to fi n d ou t wh en th e eepr o m in tern al write op eration is co m p leted . wh en th e stop co nd itio n is receiv e d and t h e eeprom starts rewriting , all o p e ra tion s are p r oh ib ited , and no respon se can b e g i v e n to t h e si g n al s se nt by t h e m a st er devi ce. t h ere f ore , i n o r de r t o find ou t wh en th e eepr o m i n tern al write op eration is co m p leted , th e start con d ition , d e v i ce address and write co mman d co d e are sen t fro m th e master d e v i ce to th e eepr o m (sl a ve devi ce ), a n d t h e resp o n se of the slave de vi ce is detected. in ot her words, if the slave de vice does no t sen d th e ackn owledg e si g n a l, it m ean s th at the in tern al write op eration is in pro g r e ss; con v e r s ely, if it do es send th e ack now ledg e si gn al, it m ean s that th e in tern al write o p e ration h a s b e en co m p leted . during write 0 1 0 1 w start no ack sda ??? 0 10 1 w start no ack 0 10 1 w start ack end of write r/w r/w r/w s1 s2 a8 during write no. 1582- 8/1 2
LE24C043 7 eeprom read operations 7-1. current address reading the address equivalent to the memory address accessed last +1 is held as the internal address of the eeprom for both write* and read operations. theref ore, provided that the master device has recognized the position of the eeprom address pointer, data can be read from the memory address with the current address pointer without specifying the word address. as with writing, current address reading involves receiving the 7-bit device address and read command code ?1? following the start condition, at which time the eeprom gene rates an acknowledge signal. after this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. after the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the eeprom completes the read operation and is set to standby mode. if the previous read address is the last address, the address for the current address reading is rolled over to become address 0. *: if the write data is 1 or more bytes but less than 16 bytes, the current address after page writing is the address equivalent to the number of bytes to be written in the specified word address +1. if the write data is 16 or more bytes, it is the designated word address. if the last address (a3-a0=1111b) on the page has been designated by byte write as the word address, the first address (a3-a0=0000b) on th e page serves as the internal address after writing. device address 0 1 0 1 r start ack no ack stop s d a d 7 d6 d5 d4 d3 d2 d1 d0 data(n+1 ) r/w s1 s2 a8 7- 2. r a n dom r ead random read i s a m ode in which a selected me m o ry addre ss is sp ecified an d its d a ta is read. the addre ss is s p ecified b y a d u m m y write in pu t. first, wh en t h e eepr o m receiv es th e 7-b it d e v i ce add r ess an d write co m m an d co d e "0 " fo llo wi n g th e start con d ition , it g e n e rates an ack nowledg e sig n a l. it th en 12 -b it wo rd a ddress a n d gene rates an ac knowledge signal. t h ese o p e ration s are u s ed to lo ad the wo rd add r ess to th e address co un ter in t h e eeprom. nex t , th e start co nd itio n is inp u t ag ain, and th e curren t read is p e rfo rm ed . th is g e n e rates th e word ad dress d a ta t h at was i n pu t u s ing th e du mmy write inpu t. after th e d a ta is gen e rated , i f th e stop co nd itio n is inp u t withou t th e i n pu t o f an ack nowledge sign al, read i n g is co m p leted , and stan db y mo d e is estab lished . d7 d6 d1 d0 ack no ack stop curre nt read r/w 0 1 0 1 w start ack sda dumm y w r ite device addr ess r/w s1 s2 a8 word address(n ) ack a7 a6 a5 a4 a3 a2 a1 a0 0 10 1 s1 s2 a8 start r device addr ess data(n ) 7- 3. se que nt i a l rea d in t h i s m ode, t h e dat a i s re ad cont i n u o u s l y , a n d se que nt i a l r ead ope rat i o ns can be per f o r m e d wi t h bot h c u r r ent a d dres s r ead and r a ndom r ead . if , af ter th e 8- b it d a ta h a s b e en o u t p u t, ackn o w l edg e ?0 ? is inp u t and r ead i n g is con tin u e d with ou t issu ing th e st o p cond itio n , th e add r ess is in crem ent e d, a n d t h e dat a of t h e ne xt ad d r ess i s o u t p ut . if ackn owledge ?0 ? con tinu e s to b e i n pu t after th e d a ta h a s b e en o u t p u t i n th is way, th e data is su ccessi vely o u t pu t while the address is inc r em ented. whe n t h e l a st address is reached, it is rol l ed ove r to address 0, and t h e data cont i n ues t o be rea d . as wi t h cur r ent a d dres s rea d a n d ra nd om read, t h e o p erat i o n i s c o m p l e t e d by i n p u t t i ng t h e st op co nd itio n wit h o u t send ing an ack nowledg e sig n a l. d7 d6 - d1 d0 data(n ) sda device addr ess 0 1 0 1 r start ack no ack stop d7 d6 - d 1 d 0 data(n+1 ) ack d7 d6 - d 1 d 0 data(n+2 ) ack d7 d6 - d1 d0 data(n+ x ) ack r/w s1 s2 a8 no. 1582- 9/1 2
LE24C043 application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + st art condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, the sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack output and read data to be output from the eeprom during the dummy clock period, forcibly entering h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. start condition dummy clock cycle 9 start condition scl sda 1 2 8 9 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin must be connected to a pull-up resistor (with a resistance from several k to several tens of k ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ?i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum resistance the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time t r and fall time t f must be set. r pu maximum value = (v dd - v ih )/i l master device eeprom sda c bus r pu i l i l example: when v dd =3.0v and i l = 2 a r pu maximum value = (3.0v ? 3.0v 0.8)/2 a = 300k r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of sanyo?s eeprom must be set. r pu minimum value = (v dd ? v ol )/i ol example: when v dd =3.0v, v ol = 0.4v and i ol = 1ma r pu minimum value = (3.0v ? 0.4)/1ma = 2.6k recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load capacitance is 50pf and the sda output data strobe time is 500ns, r pu will be about r pu = 500ns/50pf = 10k . no.1582-10/12
LE24C043 3) precautions when turning on the power this product contains a power-on reset circuit for prev enting the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. v dd =2.7 to 5.5v item symbol min typ max unit power rise time t rise 100 ms power off time t off 10 ms power bottom voltage v bot 0.2 v v dd 0v t off t rise vbot notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. a. if it is not possible to satisfy the instruction 1 in note above, and sda is set to low during power rise after the power has stabilized, the scl and sda pins must be controlled as shown below, with both pins set to high. v dd scl sda t low t dh t su.dat v dd scl sda t su.dat b. if it is not possible to satisfy the instruction 2 in note above after the power has stabilized, soft ware reset must be executed. c. if it is not possible to satisfy the instructions both 1 and 2 in note above after the power has stabilized, the steps in a must be executed, then software reset must be executed. 4) noise filter for the scl and sda pins this product contains a filter circuit for eliminating noise at the scl and sda pins. pulses of 100ns or less are not recognized because of this function. 5) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring circu it that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3v and below. 6) slave address setting this product does not include a slave address pin, but the information for the slave addresses, s1 and s2, are held internally. the slave addresses of th is product are set to s1=0, and s2=0 when it is shipped. during device addressing, execute this slave address code after the device code. no.1582-11/12
LE24C043 7) notes on write protect operation this product prohibits all memory area writing when the wp pi n is high. to ensure full write protection, the wp is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. v dd =2.7 to 5.5v item symbol min typ max unit wp setup time t su.wp 600 ns wp hold time t hd.wp 600 ns no.1582-12/12 ps this catalog provides information as of october, 2009. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. start condition stop condition scl sda t su.wp t hd.wp wp

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